I. Introduction
Recently got a LIYUTAI of 44B0X board, so I plan to own to be BOOTLOADER, on http://www.sf.net, has been found that
After it was done quite perfected. Do not think so much, and transplanted to say!
Second, download the source code
U-BOOT-1.3.2: ftp://ftp.denx.de/pub/u-boot/u-boot-1.3.2.tar.bz2
ELDK: ftp://ftp.denx.de/pub/eldk/4.1/arm-linux-x86/iso/arm-2007-01-21.iso
(Originally used by 2.95 the arm-elf-gcc to compile, but the problems are too many soft floating point,-MQ option is not supported, and so on, that's all my online
Are met. It seems their luck is good ah)
Third, extract the installation
U-BOOT-1.3.2 can directly extract
tar-jxf u-boot-1.3.2.tar.bz2
ELDK you need through a virtual drive to install. I am using the VM to run LINUX, so direct use of the virtual drive load on it. Into the CD-ROM project
Record, enter
. / Install-d / opt / eldk /
Less than five minutes to complete the installation. I remember in the / etc / profile I added the search path.
Fourth, start migration
1) a copy of the data plate B2.
Analysis found that the B2 plate with ARMSYS 44B0 of the board closest to, it started from it.
[Root @ localhost u-boot-1.3.2] # mkdir board / armsys
[Root @ localhost u-boot-1.3.2] # cp-r board / dave / * board / armsys /
[Root @ localhost u-boot-1.3.2] # mv board/armsys/B2 / board/armsys/44B0 /
[Root @ localhost u-boot-1.3.2] # mv board/armsys/44B0/B2.c board/armsys/44B0/44B0.c
[Root @ localhost u-boot-1.3.2] # cp include/configs/B2.h include/configs/44B0.h
2) modify the main Makefile, add 44B0 options
Open u-boot-1.3.2 directory Makefile, be in B2_config below to add a
44B0_config: unconfig
@ $ (MKCONFIG) $(@:_ config =) arm s3c44b0 44B0 armsys
(Remember to use TAB instead of spaces needed!)
3) modify the configuration of the CPU
Now need to modify the configuration of 44B0. U-BOOT-1.3.2 directory of the CPU has a lot of CPU to manage the classification, just change it
Can be used. We have chosen S344B0 the CPU. According LIYUTAI source code, we only need to modify the corresponding part of it.
A. modify start.s file (see LIYUTAI of BOOTLOADER)
# Include <config.h>
# Include <version.h>
//********** OPTIONS *******************************
/ / _RAM_STARTADDRESS EQU 0xc000000
# Define _ISR_STARTADDRESS 0xc7ff000 / / GCS6: 8MB SDRAM
# Define _IRQ_BASEADDRESS 0xc000000 / / GCS6: 8MB SDRAM
/ / GBLA PLLCLK
Welcome to reprint. Please keep the copyright information 1
Author: Ken Wu E-mail: kenwucn@qq.com
# Define PLLCLK 64000000
/ / The system frequency is calculated as follows:
/ / Fout = (8 + M_DIV) * Fin / [(2 + P_DIV) * 2]
# Define M_DIV 56 / / Fin = 8MHz Fout = ((56 +8) / 8) * 8 = 64MHz
# Define P_DIV 2
# Define S_DIV 1
/ *
* Jump vector table
* /
. Globl _start
_start:
b reset / / Reset
ldr pc, = (_IRQ_BASEADDRESS + 0x04) / / HandlerUndef
ldr pc, = (_IRQ_BASEADDRESS + 0x08) / / HandlerSWI
ldr pc, = (_IRQ_BASEADDRESS + 0x0C) / / HandlerPabort
ldr pc, = (_IRQ_BASEADDRESS + 0x10) / / HandlerDAbort
ldr pc, = (_IRQ_BASEADDRESS + 0x14) / / HandlerReserved
ldr pc, = (_IRQ_BASEADDRESS + 0x18) / / HandlerIRQ
ldr pc, = (_IRQ_BASEADDRESS + 0x1C) / / HandlerFIQ
. Balignl 16,0 xdeadbeef
/ *
************************************************** ***********************
*
* Startup Code (reset vector)
*
* Do important init only if we don't start from memory!
* Relocate u-boot to ram
* Setup stack
* Jump to second stage
*
************************************************** ***********************
* /
_TEXT_BASE:
. Word TEXT_BASE
. Globl _armboot_start
_armboot_start:
. Word _start
/ *
* These are defined in the board-specific linker script.
* /
. Globl _bss_start
_bss_start:
. Word __bss_start
. Globl _bss_end
_bss_end:
. Word _end
# Ifdef CONFIG_USE_IRQ
/ * IRQ stack memory (calculated at run-time) * /
. Globl IRQ_STACK_START
IRQ_STACK_START:
. Word 0x0badc0de
/ * IRQ stack memory (calculated at run-time) * /
. Globl FIQ_STACK_START
FIQ_STACK_START:
. Word 0x0badc0de
# Endif
/ *
* The actual reset code
* /
reset:
/ *
* Set the cpu to SVC32 mode
* /
mrs r0, cpsr
bic r0, r0, # 0x1f
orr r0, r0, # 0x13
msr cpsr, r0
/ *
* We do sys-critical inits only at reboot,
* Not when booting from ram!
* /
# Ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
/ *
* Before relocating, we have to setup RAM timing
* Because memory timing is board-dependend, you will
* Find a lowlevel_init.S in your board directory.
* /
bl lowlevel_init
# Endif
/ **
* Test the memory befor relocate
* /
# Ifdef CONFIG_MEM_TEST
# Define PDATE 0x1d2002c
ldr r0, = PHYS_SDRAM_1 / / address pointer
ldr r1, = PHYS_SDRAM_1_SIZE / / address of the border
add r1, r0, r1 / / r1 is the bound
ldr r3, = 0xAA55AA44
loop:
str r3, [r0] / / save data to memory
ldr r4, [r0] / / re-read data
cmp r4, r3 / / compare data
bne error
add r0, r0, # 4 / / pointer to point to the next
cmp r0, r1 / / determine whether to reach the border
beq mem_test_ok
bne loop
error:
ldr r0, = PDATE / / PDATE = PDATE &0x1f7;
ldr r1, [r0]
ldr r2, = 0x1f7
and r1, r1, r2
str r1, [r0]
bl delay / / Beep
ldr r1, [r0] / / PDATE = PDATE | 0x8;
mov r2, # 0x8
orr r1, r1, r2
str r1, [r0]
bl delay / / stop Beep
end:
b end / / stop
delay:
ldr r3, = 0xFFFF
e_loop1:
sub r3, r3, # 1
cmp r3, # 0
beq loop_end
ldr r4, = 0xFF
e_loop2:
sub r4, r4, # 1
cmp r4, # 0
bne e_loop2
b e_loop1
loop_end:
mov pc, lr
mem_test_ok:
# Endif
# Ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: / * relocate U-Boot to RAM * /
adr r0, _start / * r0 <- current position of code * /
ldr r1, _TEXT_BASE / * test if we run from flash or RAM * /
cmp r0, r1 / * don't reloc during debug * /
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 / * r2 <- size of armboot * /
add r2, r0, r2 / * r2 <- source end address * /
copy_loop:
ldmia r0!, {r3-r10} / * copy from source address [r0] * /
stmia r1!, {r3-r10} / * copy to target address [r1] * /
cmp r0, r2 / * until source end addreee [r2] * /
ble copy_loop
/ *
now copy to sram the interrupt vector
* /
adr r0, real_vectors
add r2, r0, # 1024
ldr r1, = 0x0c000000
add r1, r1, # 0x08
vector_copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
ble vector_copy_loop
# Endif / * CONFIG_SKIP_RELOCATE_UBOOT * /
Welcome to reprint. Please keep the copyright information 5
Author: Ken Wu E-mail: kenwucn@qq.com
/ * Set up the stack * /
stack_setup:
ldr r0, _TEXT_BASE / * upper 128 KiB: relocated uboot * /
sub r0, r0, # CFG_MALLOC_LEN / * malloc area * /
sub r0, r0, # CFG_GBL_DATA_SIZE / * bdinfo * /
# Ifdef CONFIG_USE_IRQ
sub r0, r0, # (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
# Endif
sub sp, r0, # 12 / * leave 3 words for abort-stack * /
clear_bss:
/ * BSS segment start address * /
ldr r0, _bss_start
/ * BSS segment end address * /
ldr r1, _bss_end
/ * BSS segment set to 0 * /
mov r2, # 0x00000000
clbss_l:
/ * Clear BSS section loop * /
str r2, [r0]
add r0, r0, # 4
cmp r0, r1
ble clbss_l
ldr pc, _start_armboot
_start_armboot:. word start_armboot
/ *
************************************************** ***********************
*
* CPU_init_critical registers
*
* Setup important registers
* Setup memory timing
*
************************************************** ***********************
* /
# Define INTCON (0x01c00000 +0 x200000)
# Define INTMSK (0x01c00000 +0 x20000c)
# Define LOCKTIME (0x01c00000 +0 x18000c)
# Define PLLCON (0x01c00000 +0 x180000)
# Define CLKCON (0x01c00000 +0 x180004)
# Define WTCON (0x01c00000 +0 x130000)
cpu_init_crit:
/ * Disable watch dog * /
ldr r0, = WTCON
ldr r1, = 0x0
str r1, [r0]
/ *
* Mask all IRQs by clearing all bits in the INTMRs
* /
ldr r1, = INTMSK
ldr r0, = 0x07fffeff
str r0, [r1]
ldr r1, = INTCON
ldr r0, = 0x05
str r0, [r1]
/ * Set Clock Control Register * /
ldr r0, = LOCKTIME
ldr r1, = 0xfff
str r1, [r0]
ldr r1, = PLLCON
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
ldr r0, = 0x34031 / * 66MHz (Quartz = 11MHz) * /
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
ldr r0, = 0x610c1 / * B2: Xtal = 20mhz Fclk = 75MHz * /
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
ldr r0, = 0x38021 / / Fin = 8MHz, Fout = 64MHz
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif
str r0, [r1]
ldr r1, = CLKCON
ldr r0, = 0x7ff8
str r0, [r1]
mov pc, lr
/************************************************* /
/ * Interrupt vectors * /
/************************************************* /
real_vectors:
b reset
b undefined_instruction
b software_interrupt
b prefetch_abort
b data_abort
b not_used
b irq
b fiq
/************************************************* /
undefined_instruction:
mov r6, # 3
b reset
software_interrupt:
mov r6, # 4
b reset
prefetch_abort:
mov r6, # 5
b reset
data_abort:
mov r6, # 6
b reset
not_used:
/ * We * should * never reach this * /
mov r6, # 7
b reset
irq:
mov r6, # 8
b reset
fiq:
mov r6, # 9
b reset
B. modify serial.c, modify serial_setbrg. Function as the board's baud rate to use 64MHz, so the need to increase the corresponding baud rate configurations
void serial_setbrg (void)
{
u32 divisor = 0;
/ * Get correct divisor * /
switch (gd-> baudrate) {
case 1200:
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
divisor = 3124;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
divisor = 3905;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
divisor = 3124;
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif
break;
case 9600:
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
divisor = 390;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
divisor = 487;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
divisor = 390;
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif
break;
case 19200:
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
divisor = 194;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
divisor = 243;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
divisor = 194;
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif
break;
case 38400:
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
divisor = 97;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
divisor = 121;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
divisor = 97;
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif / * break; * /
case 57600:
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
divisor = 64;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
divisor = 80;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
divisor = 68;
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif / * break; * /
case 115200:
# If CONFIG_S3C44B0_CLOCK_SPEED == 66
divisor = 32;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 75
divisor = 40;
# Elif CONFIG_S3C44B0_CLOCK_SPEED == 64
divisor = 34;
# Else
# Error CONFIG_S3C44B0_CLOCK_SPEED undefined
# Endif / * break; * /
}
serial_flush_output ();
serial_flush_input ();
UFCON0 = 0x0;
ULCON0 = 0x03;
UCON0 = 0x245;
UBRDIV0 = divisor;
UFCON1 = 0x0;
ULCON1 = 0x03;
UCON1 = 0x245;
UBRDIV1 = divisor;
for (divisor = 0; divisor <100; divisor + +) {
/ * NOP * /
}
}
At this point, CPU configuration is complete. Next, modify the board configuration.
Into armsys/44B0 folder, start the configuration 44B0 board.
4)
A. modify lowlevel_init.S. lowlevel_init.S is related to external devices to read and write timing, the delay of the configuration file, you can use LIYUTAI of
(LIYUTAI RAM configuration is not very good, but just be able to spend just a little more slowly.)
Configured on it.
. Equ B0_Tacs, 0x0 / * 0clk * /
. Equ B0_Tcos, 0x1 / * 0clk * /
. Equ B0_Tacc, 0x6 / * 10clk * /
. Equ B0_Tcoh, 0x1 / * 0clk * /
. Equ B0_Tah, 0x0 / * 0clk * /
. Equ B0_Tacp, 0x0 / * 0clk * /
. Equ B0_PMC, 0x0 / * normal (1data) * /
/ * Bank 1 parameter * /
. Equ B1_Tacs, 0x3 / * 4clk * /
. Equ B1_Tcos, 0x3 / * 4clk * /
. Equ B1_Tacc, 0x7 / * 14clkv * /
. Equ B1_Tcoh, 0x3 / * 4clk * /
. Equ B1_Tah, 0x3 / * 4clk * /
. Equ B1_Tacp, 0x3 / * 6clk * /
. Equ B1_PMC, 0x0 / * normal (1data) * /
/ * Bank 2 parameter * /
. Equ B2_Tacs, 0x3 / * 4clk * /
. Equ B2_Tcos, 0x3 / * 4clk * /
. Equ B2_Tacc, 0x7 / * 14clk * /
. Equ B2_Tcoh, 0x3 / * 4clk * /
. Equ B2_Tah, 0x3 / * 4clk * /
. Equ B2_Tacp, 0x3 / * 6clk * /
. Equ B2_PMC, 0x0 / * normal (1data) * /
/ * Bank 3 parameter * /
. Equ B3_Tacs, 0x3 / * 4clk * /
. Equ B3_Tcos, 0x3 / * 4clk * /
. Equ B3_Tacc, 0x7 / * 14clk * /
. Equ B3_Tcoh, 0x3 / * 4clk * /
. Equ B3_Tah, 0x3 / * 4clk * /
. Equ B3_Tacp, 0x3 / * 6clk * /
. Equ B3_PMC, 0x0 / * normal (1data) * /
/ * Bank 4 parameter * /
. Equ B4_Tacs, 0x3 / * 4clk * /
. Equ B4_Tcos, 0x3 / * 4clk * /
. Equ B4_Tacc, 0x7 / * 14clk * /
. Equ B4_Tcoh, 0x3 / * 4clk * /
. Equ B4_Tah, 0x3 / * 4clk * /
. Equ B4_Tacp, 0x3 / * 6clk * /
. Equ B4_PMC, 0x0 / * normal (1data) * /
/ * Bank 5 parameter * /
. Equ B5_Tacs, 0x3 / * 4clk * /
. Equ B5_Tcos, 0x3 / * 4clk * /
. Equ B5_Tacc, 0x7 / * 14clk * /
. Equ B5_Tcoh, 0x3 / * 4clk * /
. Equ B5_Tah, 0x3 / * 4clk * /
. Equ B5_Tacp, 0x3 / * 6clk * /
. Equ B5_PMC, 0x0 / * normal (1data) * /
/ * Bank 6 (if SROM) parameter * /
. Equ B6_Tacs, 0x3 / * 4clk * /
. Equ B6_Tcos, 0x3 / * 4clk * /
. Equ B6_Tacc, 0x7 / * 14clk * /
. Equ B6_Tcoh, 0x3 / * 4clk * /
. Equ B6_Tah, 0x3 / * 4clk * /
. Equ B6_Tacp, 0x3 / * 6clk * /
. Equ B6_PMC, 0x0 / * normal (1data) * /
/ * Bank 7 (if SROM) parameter * /
. Equ B7_Tacs, 0x3 / * 4clk * /
. Equ B7_Tcos, 0x3 / * 4clk * /
. Equ B7_Tacc, 0x7 / * 14clk * /
. Equ B7_Tcoh, 0x3 / * 4clk * /
. Equ B7_Tah, 0x3 / * 4clk * /
. Equ B7_Tacp, 0x3 / * 6clk * /
. Equ B7_PMC, 0x0 / * normal (1data) * /
/ * Bank 6 parameter * /
. Equ B6_MT, 0x3 / * SDRAM * /
. Equ B6_Trcd, 0x1 / * 2clk * /
. Equ B6_SCAN, 0x0 / * 10bit * /
. Equ B7_MT, 0x3 / * SDRAM * /
. Equ B7_Trcd, 0x1 / * 2clk * /
. Equ B7_SCAN, 0x0 / * 10bit * /
/ * REFRESH parameter * /
. Equ REFEN, 0x1 / * Refresh enable * /
. Equ TREFMD, 0x0 / * CBR (CAS before RAS) / Auto refresh * /
. Equ Trp, 0x1 / * 2clk * /
. Equ Trc, 0x1 / * 0x1 = 5clk 0x3 = 11clk * /
. Equ Tchr, 0x2 / * 0x2 = 3clk 0x0 = 0clks * /
. Equ REFCNT, 1050 / /; period = 15.6us, MCLK = 64Mhz
MEMORY_CONFIG:
. Long 0x11010101 / * Bank0 = OM [1:0], Bank1-7 16bit, Bank2 = Nowait, UB / LB * /
. Word
((B0_Tacs <<13) + (B0_Tcos <<11) + (B0_Tacc <<8) + (B0_Tcoh <<6) + (B0_Tah <<4) + (B0_Tacp <<2) + (B0_PMC))
/ * GCS0 * /
. Word
((B1_Tacs <<13) + (B1_Tcos <<11) + (B1_Tacc <<8) + (B1_Tcoh <<6) + (B1_Tah <<4) + (B1_Tacp <<2) + (B1_PMC))
/ * GCS1 * /
. Word
((B2_Tacs <<13) + (B2_Tcos <<11) + (B2_Tacc <<8) + (B2_Tcoh <<6) + (B2_Tah <<4) + (B2_Tacp <<2) + (B2_PMC))
/ * GCS2 * /
. Word
((B3_Tacs <<13) + (B3_Tcos <<11) + (B3_Tacc <<8) + (B3_Tcoh <<6) + (B3_Tah <<4) + (B3_Tacp <<2) + (B3_PMC))
/ * GCS3 * /
. Word
((B4_Tacs <<13) + (B4_Tcos <<11) + (B4_Tacc <<8) + (B4_Tcoh <<6) + (B4_Tah <<4) + (B4_Tacp <<2) + (B4_PMC))
/ * GCS4 * /
. Word
((B5_Tacs <<13) + (B5_Tcos <<11) + (B5_Tacc <<8) + (B5_Tcoh <<6) + (B5_Tah <<4) + (B5_Tacp <<2) + (B5_PMC))
/ * GCS5 * /
. Word ((B6_MT <<15) + (B6_Trcd <<2) + (B6_SCAN)) / * GCS6 * /
. Word ((B7_MT <<15) + (B7_Trcd <<2) + (B7_SCAN)) / * GCS7 * /
. Word ((REFEN <<23) + (TREFMD <<22) + (Trp <<20) + (Trc <<18) + (Tchr <<16) + REFCNT) / * REFRESH RFEN = 1,
TREFMD = 0, trp = 3clk, trc = 5clk, tchr = 3clk, count = 1019 * /
. Word 0x17 / * SCLK power down mode, BANKSIZE 16M/16M * /
. Word 0x20 / * MRSR6 CL = 2clk * /
. Word 0x20 / * MRSR7 * /
B. modify the files inside the board_init 44B0.c function, this function is U-BOOT to complete initialization after entering the bottom of the first C function.
int board_init (void)
{
/ / CAUTION: Follow the configuration order for setting the ports.
/ / 1) setting value
/ / 2) setting control register
/ / 3) configure pull-up resistor.
/ / 16bit data bus configuration
/ / PORT A GROUP
/ * BIT 98 7 6 5 4 3 2 1 0 * /
/ * A24 A23 A22 A21 A20 A19 A18 A17 A16 A0 * /
/ * 1111111111 * /
PCONA = 0x3ff;
/ / PORT B GROUP
/ * BIT 10 9 8 7 6 5 4 3 2 1 0
* /
/ * / CS5 / CS4 / CS3 / CS2 / CS1 nWBE3 nWBE2 / SRAS / SCAS SCLK SCKE
* /
/ * EXT NIC USB IDE SMC NC NC Sdram Sdram Sdram
Sdram * /
/ * 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 * /
PDATB = 0x7ff;
PCONB = 0x7cf;
/ / PORT C GROUP
/ / BUSWIDTH = 16 * /
/ * PC15 14 13 12 11 10 9 8 * /
/ * IO RXD1 TXD1 IIII * /
/ * PS2DAT DCLK Uart1 Uart1 NC NC NC NC * /
/ * 0,001,111,100,000,000 * /
/ * PC7 6 5 4 3 2 1 0 * /
/ * IIIIIIII * /
/ * VD4 VD5 VD6 VD7 SMCALE SMCCLE SMCCE SMCRB * /
/ * 0,000,000,001,010,100 * /
PDATC = 0xffff; / / All IO is high
PCONC = 0x1f05ff54;
PUPC = 0x3000; / / PULL UP RESISTOR should be enabled to I / O
/ / PORT D GROUP
/ * PORT D GROUP (I / O OR LCD) * /
/ * BIT 7 6 5 4 3 2 1 0 * /
/ * VF VM VLINE VCLK VD3 VD2 VD1 VD0 * /
/ * 0,000,000,000,000,000 * /
PDATD = 0xff;
PCOND = 0xaaaa;
PUPD = 0x0;
/ / These pins must be set only after CPU's internal LCD controller is enable
/ / PORT E GROUP
/ * Bit 8 7 6 5 4 3 2 1 0 * /
/ * LcdBL LED4 LED5 LED6 LED7 BEEP RXD0 TXD0 LcdDisp * /
/ * 01 0,101,010,101,101,001 * /
PDATE = 0x1ff;
PCONE = 0x25569;
PUPE = 0x6;
/ / PORT F GROUP
/ * Bit8 7 6 5 4 3 2 1 0 * /
/ * IISCLK IISDI IISDO IISLRCK Input Input Input IICSDA IICSCL * /
/ * 100 1,001,001,000,000,001,010 * /
PDATF = 0x0;
PCONF = 0x24900a;
PUPF = 0x1e3;
/ / PORT G GROUP
/ * BIT7 6 5 4 3 2 1 0 * /
/ * INT7 INT6 INT5 INT4 INT3 INT2 INT1
INT0 * /
/ * S3 S4 S5 S6 NIC EXT IDE USB * /
/ * 1,111,111,111,111,111 * /
/ / RPDATG = 0xff;
/ / RPCONG = 0xffff;
PCONG = 0x00ff; / / EXINT0 ~ 3 enabled
PUPG = 0x0; / / pull-up regiseter should be enabled
SPUCR = 0x7; / / D15-D0 pull-up disable
/ * Are low-level trigger, Exint3 set to rising edge ---- modify at 04-12-11 * /
EXTINT = 0x0 | (1 <<14);
return 0;
}
Can be used directly LIYUTAI port initialization function instead on it.
Modify the Makefile to replace 44B0.o B2.o
C.
Modify config.mk file, change the value of the TEXT_BASE 0x0C300000. This is only 2M order to leave space to download the kernel.
D.
U-BOOT boot code will copy TEXT_BASE position, if you do not modify this value, the code will download the larger dead
Machine.
Modify board / armsys / common / flash.c configuration, add flash support.
E.
flash.c:
case (CFG_FLASH_WORD_SIZE) SST_ID_xF160A:
case (CFG_FLASH_WORD_SIZE) SST_ID_xF1601:
And replace all the B2 as 44B0, so as to build into it at compile time
At this point, 44B0 board has been configured. Then you modify configuration files.
Modify include/configs/44B0.h file.
5)
The following is my entire 44B0.h profile
# Ifndef __CONFIG_H
# Define __CONFIG_H
/ *
* High Level Configuration Options
* (Easy to change)
* /
# Define CONFIG_ARM7 1 / * This is a ARM7 CPU * /
# Define CONFIG_44B0 1 / * on an 44B0 Board * /
# Define CONFIG_ARM_THUMB 1 / * this is an ARM7TDMI * /
# Undef CONFIG_ARM7_REVD / * disable ARM720 REV.D Workarounds * /
# Define CONFIG_S3C44B0_CLOCK_SPEED 64 / * we have a 75Mhz S3C44B0 * /
/ / # Define CONFIG_MEM_TEST / / do ram test
# Define CONFIG_SILENT_CONSOLE 1 / / config with silent
# Undef CONFIG_USE_IRQ / * don't need them anymore * /
/ *
* Size of malloc () pool
* /
# Define CFG_MONITOR_LEN (256 * 1024) / * Reserve 256 kB for Monitor * /
# Define CFG_ENV_SIZE 1024 / * 1024 bytes may be used for env vars * /
# Define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
# Define CFG_GBL_DATA_SIZE 128 / * size in bytes reserved for initial data * /
/ *
* Hardware drivers
* /
/ / # Define CONFIG_DRIVER_LAN91C96
/ / # Define CONFIG_LAN91C96_BASE 0x04000300 / * base address * /
/ / # Define CONFIG_SMC_USE_32_BIT
/ / # Undef CONFIG_SHOW_ACTIVITY
/ / # Define CONFIG_NET_RETRY_COUNT 10 / * # of retries * /
# Define CONFIG_DRIVER_RTL8019
# Define RTL8019_BASE 0x08000000
/ / # Define ET_DEBUG / / DEBUG the ethernet
/ *
* Select serial console configuration
* /
# Define CONFIG_SERIAL1 1 / * we use Serial line 1 * /
/ * Allow to overwrite serial and ethaddr * /
# Define CONFIG_ENV_OVERWRITE
# Define CONFIG_BAUDRATE 115200
/ *
* BOOTP options
* /
# Define CONFIG_BOOTP_SUBNETMASK
# Define CONFIG_BOOTP_GATEWAY
# Define CONFIG_BOOTP_HOSTNAME
# Define CONFIG_BOOTP_BOOTPATH
# Define CONFIG_BOOTP_BOOTFILESIZE
/ *
* Command line configuration.
* /
# Include <config_cmd_default.h>
# Define CONFIG_CMD_DATE
# Define CONFIG_CMD_ELF
/ / # Define CONFIG_CMD_EEPROM
/ / # Define CONFIG_CMD_I2C
# Define CONFIG_CMD_PING / / ping cmd enable
# Define CONFIG_CMD_FLASH / / nor flash support
/ / # Define CONFIG_CMD_NAND / / nand flash support
# Define CONFIG_BOOTDELAY 1
# Define CONFIG_ETHADDR 00:50: c2: 1e: af: fb
# Define CONFIG_BOOTARGS "setenv bootargs root = / dev / ram ip = 192.168.1000.70 ::::: eth0: off \
ether = 25,0,0,0, eth0 ethaddr = 00:50: c2: 1e: af: fb "
# Define CONFIG_NETMASK 255.255.255.0
# Define CONFIG_IPADDR 192.168.100.70
# Define CONFIG_SERVERIP 192.168.100.163
# Define CONFIG_BOOTFILE "image.ram"
/ / # Define CONFIG_BOOTCOMMAND "bootm 20000 f0000"
/ / # Define CONFIG_BOOTCOMMAND "base 0" / / for debuging
# Define CONFIG_BOOTCOMMAND "?" / / For debuging
/ *
* Miscellaneous configurable options
* /
# Define CFG_LONGHELP / * undef to save memory * /
# Define CFG_PROMPT "U-Boot (Ken Wu)>" / * Monitor Command Prompt * /
# Define CFG_CBSIZE 256 / * Console I / O Buffer Size * /
# Define CFG_PBSIZE (CFG_CBSIZE + sizeof (CFG_PROMPT) +16) / * Print Buffer Size * /
# Define CFG_MAXARGS 16 / * max number of command args * /
# Define CFG_BARGSIZE CFG_CBSIZE / * Boot Argument Buffer Size * /
# Define CFG_MEMTEST_START0x0C400000 / * memtest works on * /
# Define CFG_MEMTEST_END 0x0C800000 / * 4 ... 8 MB in DRAM * /
# Undef CFG_CLKS_IN_HZ / * everything, incl board info, in Hz * /
# Define CFG_LOAD_ADDR 0x0c008000 / * default load address * /
# Define CFG_HZ 1000 / * 1 kHz * /
/ * Valid baudrates * /
# Define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/*------------------------------------------------ -----------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
* /
# Define CONFIG_STACKSIZE (128 * 1024) / * regular stack * /
# Ifdef CONFIG_USE_IRQ
# Define CONFIG_STACKSIZE_IRQ (4 * 1024) / * IRQ stack * /
# Define CONFIG_STACKSIZE_FIQ (4 * 1024) / * FIQ stack * /
# Endif
/*------------------------------------------------ -----------------------
* Physical Memory Map
* /
# Define CONFIG_NR_DRAM_BANKS 1 / * we have 1 banks of DRAM * /
# Define PHYS_SDRAM_1 0x0C000000 / * SDRAM Bank # 1 * /
# Define PHYS_SDRAM_1_SIZE 0x00800000 / * 8 MB * /
/ / # Define CONFIG_HAS_DATAFLASH / / we have flash
# Define PHYS_FLASH_1 0x00000000 / * Flash Bank # 1 * /
# Define PHYS_FLASH_SIZE 0x00200000 / * 2 MB * /
/ / # Define CFG_FLASH_BASE PHYS_FLASH_1
/*------------------------------------------------ -----------------------
* FLASH and environment organization
* /
/*------------------------------------------------ -----------------------
* FLASH organization
* /
# Define CFG_MAX_FLASH_BANKS 1 / * max number of memory banks * /
# Define CFG_MAX_FLASH_SECT 32 / * max number of sectors on one chip * /
# Define FLASH_BLOCK_SIZE 0x00010000 / / flash block size
# Define CFG_FLASH_ERASE_TOUT 120000 / * Timeout for Flash Erase (in ms) * /
# Define CFG_FLASH_WRITE_TOUT 1000 / * Timeout for Flash Write (in ms) * /
# Define CFG_FLASH_WORD_SIZE unsigned short / * flash word size (width) * /
# Define CFG_FLASH_ADDR0 0x5555 / * 1st address for flash config cycles * /
# Define CFG_FLASH_ADDR1 0x2AAA / * 2nd address for flash config cycles * /
/ *
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
* /
# Define CFG_FLASH_READ0 0x0000 / * 0 is standard * /
# Define CFG_FLASH_READ1 0x0001 / * 1 is standard * /
# Define CFG_FLASH_READ2 0x0002 / * 2 is standard * /
# Define CFG_FLASH_EMPTY_INFO / * print 'E' for empty sector on flinfo * /
/ **
* NAND flash organization & operation
* /
# If defined (CONFIG_CMD_NAND)
# Define NAND_DEBUG 1 / / debug the nand info
# Define CFG_NAND_LEGACY
# Define CFG_NAND_BASE 0x02000000
# Define CFG_MAX_NAND_DEVICE 1 / * Max number of NAND devices * /
# Define SECTORSIZE 512
# Define ADDR_COLUMN 1
# Define ADDR_PAGE 2
# Define ADDR_COLUMN_PAGE 3
# Define NAND_ChipID_UNKNOWN 0x00
# Define NAND_MAX_FLOORS 1
# Define NAND_MAX_CHIPS 1
# Define NAND_WAIT_READY (nand) WAIT_RB ()
# Define NAND_DISABLE_CE (nand) ST_INVALID ()
# Define NAND_ENABLE_CE (nand)
# Define WRITE_NAND_COMMAND (d, adr) NAND_write_cmd (d)
/ / # Define WRITE_NAND_COMMANDW (d, adr) NF_CmdW (d)
# Define WRITE_NAND_ADDRESS (d, adr) NAND_write_addr (d)
# Define WRITE_NAND (d, adr) NAND_write (d)
# Define READ_NAND (adr) NAND_read ()
/ *
* The following functions are NOP's because S3C24X0 handles this in hardware
* But it must define in S344B0 board because the board does not support the interface
* /
# Define NAND_CTL_CLRALE (nandptr)
# Define NAND_CTL_SETALE (nandptr)
# Define NAND_CTL_SETCLE (nandptr)
/ / Do not use write verify and jffs2 ecc at first
/ / # Define CONFIG_MTD_NAND_VERIFY_WRITE 1
/ / # Define CONFIG_MTD_NAND_ECC_JFFS2 1
# Endif
/*------------------------------------------------ -----------------------
* Environment Variable setup
* /
/ / # Define CFG_ENV_IS_IN_EEPROM 1 / * use EEPROM for environment vars * /
/ / # Define CFG_ENV_OFFSET 0x0 / * environment starts at the beginning of the EEPROM * /
# Define CFG_ENV_IS_IN_FLASH 1
# Undef CFG_ENV_IS_NOWHERE
# Define CFG_FLASH_BASE PHYS_FLASH_1
/ / Start from 0x10000 to save the system parameters at
# Define CFG_ENV_OFFSET 0x100000
/ / # Define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x20000) / * environment start address * /
# Define CFG_ENV_SECT_SIZE 0x10000 / * Total Size of Environment Sector * /
/ / # Define CFG_MONITOR_BASE PHYS_SDRAM_1
/*------------------------------------------------ -----------------------
* I2C EEPROM (STM24C02W6) for environment
* /
/ / # Define CONFIG_HARD_I2C / * I2c with hardware support * /
/ / # Define CFG_I2C_SPEED 400000 / * I2C speed and slave address * /
/ / # Define CFG_I2C_SLAVE 0xFE
/ /
/ / # Define CFG_I2C_EEPROM_ADDR 0xA8 / * EEPROM STM24C02W6 * /
/ / # Define CFG_I2C_EEPROM_ADDR_LEN 1 / * Bytes of address * /
/ / / * Mask of address bits that overflow into the "EEPROM chip address" * /
///*# Define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 * /
/ / # Define CFG_EEPROM_PAGE_WRITE_BITS 4 / * The Catalyst CAT24WC08 has * /
/ * 16 byte page write mode using * /
/ * Last 4 bits of the address * /
/ / # Define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 / * and takes up to 10 msec * /
/ / # Define CFG_EEPROM_PAGE_WRITE_ENABLE
/ * Flash banks JFFS2 should use * /
/ *
# Define CFG_JFFS2_FIRST_BANK 0
# Define CFG_JFFS2_FIRST_SECTOR 2
# Define CFG_JFFS2_NUM_BANKS 1
* /
/ *
Linux TAGs (see lib_arm / armlinux.c)
* /
# Define CONFIG_CMDLINE_TAG
# Undef CONFIG_SETUP_MEMORY_TAGS
# Define CONFIG_INITRD_TAG
# Endif / * __CONFIG_H * /
At this point, the configuration has been completed, you can make out the image to the!! ☺
make image
6)
make 44B0_config
make CROSS_COMPILE = arm-linux-
(A lot of compiled information drifting away...)
Finally, you can see the u-boot.bin image files. Burned into the flash which can be directly run! ^ _ ^
Fifth, increased network support
Because linux is there are hundreds of moving image k, if every time you use the serial port to transfer too slow. LIYUTAI board using RTL8019,
U-BOOT have driven directly above, as long as you can change it with a! (Ecstasy!!!)
1) Modify drivers/net/rtl8019.h
# Include <asm/types.h>
# Include <config.h>
# Ifdef CONFIG_DRIVER_RTL8019
# Define ETH_ADDR_SFT (8)
# Define EI_SHIFT (x) ((x) <<ETH_ADDR_SFT)
# Define RTL8019_REG_00 (RTL8019_BASE + EI_SHIFT (0x00))
# Define RTL8019_REG_01 (RTL8019_BASE + EI_SHIFT (0x01))
# Define RTL8019_REG_02 (RTL8019_BASE + EI_SHIFT (0x02))
# Define RTL8019_REG_03 (RTL8019_BASE + EI_SHIFT (0x03))
# Define RTL8019_REG_04 (RTL8019_BASE + EI_SHIFT (0x04))
# Define RTL8019_REG_05 (RTL8019_BASE + EI_SHIFT (0x05))
# Define RTL8019_REG_06 (RTL8019_BASE + EI_SHIFT (0x06))
# Define RTL8019_REG_07 (RTL8019_BASE + EI_SHIFT (0x07))
# Define RTL8019_REG_08 (RTL8019_BASE + EI_SHIFT (0x08))
# Define RTL8019_REG_09 (RTL8019_BASE + EI_SHIFT (0x09))
# Define RTL8019_REG_0a (RTL8019_BASE + EI_SHIFT (0x0a))
# Define RTL8019_REG_0b (RTL8019_BASE + EI_SHIFT (0x0b))
# Define RTL8019_REG_0c (RTL8019_BASE + EI_SHIFT (0x0c))
# Define RTL8019_REG_0d (RTL8019_BASE + EI_SHIFT (0x0d))
# Define RTL8019_REG_0e (RTL8019_BASE + EI_SHIFT (0x0e))
# Define RTL8019_REG_0f (RTL8019_BASE + EI_SHIFT (0x0f))
# Define RTL8019_REG_10 (RTL8019_BASE + EI_SHIFT (0x10))
# Define RTL8019_REG_1f (RTL8019_BASE + EI_SHIFT (0x1f))
# Define RTL8019_COMMAND RTL8019_REG_00
# Define RTL8019_PAGESTART RTL8019_REG_01
# Define RTL8019_PAGESTOP RTL8019_REG_02
# Define RTL8019_BOUNDARY RTL8019_REG_03
# Define RTL8019_TRANSMITSTATUS RTL8019_REG_04
# Define RTL8019_TRANSMITPAGE RTL8019_REG_04
# Define RTL8019_TRANSMITBYTECOUNT0RTL8019_REG_05
# Define RTL8019_NCR RTL8019_REG_05
# Define RTL8019_TRANSMITBYTECOUNT1 RTL8019_REG_06
# Define RTL8019_INTERRUPTSTATUS RTL8019_REG_07
# Define RTL8019_CURRENT RTL8019_REG_07
# Define RTL8019_REMOTESTARTADDRESS0 RTL8019_REG_08
# Define RTL8019_CRDMA0 RTL8019_REG_08
# Define RTL8019_REMOTESTARTADDRESS1 RTL8019_REG_09
# Define RTL8019_CRDMA1 RTL8019_REG_09
# Define RTL8019_REMOTEBYTECOUNT0 RTL8019_REG_0a
# Define RTL8019_REMOTEBYTECOUNT1 RTL8019_REG_0b
# Define RTL8019_RECEIVESTATUS RTL8019_REG_0c
# Define RTL8019_RECEIVECONFIGURATION RTL8019_REG_0c
# Define RTL8019_TRANSMITCONFIGURATION RTL8019_REG_0d
# Define RTL8019_FAE_TALLY RTL8019_REG_0d
# Define RTL8019_DATACONFIGURATION RTL8019_REG_0e
# Define RTL8019_CRC_TALLY RTL8019_REG_0e
# Define RTL8019_INTERRUPTMASK RTL8019_REG_0f
# Define RTL8019_MISS_PKT_TALLY RTL8019_REG_0f
# Define RTL8019_PHYSICALADDRESS0 RTL8019_REG_01
# Define RTL8019_PHYSICALADDRESS1 RTL8019_REG_02
# Define RTL8019_PHYSICALADDRESS2 RTL8019_REG_03
# Define RTL8019_PHYSICALADDRESS3 RTL8019_REG_04
# Define RTL8019_PHYSICALADDRESS4 RTL8019_REG_05
# Define RTL8019_PHYSICALADDRESS5 RTL8019_REG_06
# Define RTL8019_MULTIADDRESS0 RTL8019_REG_08
# Define RTL8019_MULTIADDRESS1 RTL8019_REG_09
# Define RTL8019_MULTIADDRESS2 RTL8019_REG_0a
# Define RTL8019_MULTIADDRESS3 RTL8019_REG_0b
# Define RTL8019_MULTIADDRESS4 RTL8019_REG_0c
# Define RTL8019_MULTIADDRESS5 RTL8019_REG_0d
# Define RTL8019_MULTIADDRESS6 RTL8019_REG_0e
# Define RTL8019_MULTIADDRESS7 RTL8019_REG_0f
# Define RTL8019_DMA_DATA RTL8019_REG_10
# Define RTL8019_RESET RTL8019_REG_1f
# Define RTL8019_PAGE0 0x22
# Define RTL8019_PAGE1 0x62
# Define RTL8019_PAGE0DMAWRITE 0x12
# Define RTL8019_PAGE2DMAWRITE 0x92
# Define RTL8019_REMOTEDMAWR 0x12
# Define RTL8019_REMOTEDMARD 0x0A
# Define RTL8019_ABORTDMAWR 0x32
# Define RTL8019_ABORTDMARD 0x2A
# Define RTL8019_PAGE0STOP 0x21
# Define RTL8019_PAGE1STOP 0x61
# Define RTL8019_TRANSMIT 0x26
# Define RTL8019_TXINPROGRESS 0x04
# Define RTL8019_SEND 0x1A
# Define RTL8019_PSTART 0x4c
# Define RTL8019_PSTOP 0x80
# Define RTL8019_TPSTART 0x40
# Endif / * end of CONFIG_DRIVER_RTL8019 * /
Modify drivers/net/rtl8019.c
2)
When debugging the network has been unreasonable, and later found out after debugging is rtl8019.c a problem. There do not know why put_reg function
volatile and get_reg not, the question arises here. Add to, OK!
static unsigned char get_reg (unsigned int regno)
{
return (* (volatile unsigned char *) regno);
}
VI debugging U-BOOT
In order to debug U-BOOT, I really detail the way, try a good variety of methods can not be source-level debugging. Was found with RVDK
You can debug the window below, as follows: (skyeye later found out that you can use to debug, even on the board can not! Thank you
skyeye of doing such a good platform for us to provide)
Modify arm_config.mk file, add-gdwarf options
# PLATFORM_CPPFLAGS + =-DCONFIG_ARM-D__ARM__
# Debug
PLATFORM_CPPFLAGS + =-DCONFIG_ARM-D__ARM__-gdwarf-2
Then the above can be carried out in RVDK source-level debugging. It was great ~ ~ ~
VII Postscript
In the Portable Document to thank samfei
(Http://www.linuxforum.net/forum/showflat.php?Cat=&Board=embedded&Number=566316&page=&view=&sb=&o
= & Vc = 1), according to basically be able to complete u-boot-1.1.6. I ported it to 1.3.2, hope to help novice.
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