NAND Flash memory devices are designed for applications requiring nonvolatile, highdensity,
solid-state storage media. Historically, NAND Flash has been used extensively in
applications such as mass storage cards and digital cameras. With its low cost and high
performance, NAND Flash is beginning to make its way into more complex embedded
systems where NOR Flash has dominated in the past—for example, in mobile phones.
In complex embedded systems, one of the challenges associated with a change from
NOR Flash to NAND Flash has been the boot process. NOR Flash has been a popular
choice for these systems because it contains a traditional memory interface (including
both address and data buses), making it capable of execute-in-place (XIP) operation. XIP
memory enables the system CPU to execute code directly from the memory device
because the boot code is stored on and executed from a single device.
NAND Flash is a page-oriented memory device that does not inherently support XIP, at
least not in the same manner as a typical XIP memory device. Operating system and
boot code can be stored in NAND Flash memory, but the code must be copied (or shadowed)
to DRAM before it can be executed. This requires system designers to modify the
boot process for their systems when using NAND Flash. The payoff for this modification
is that the system benefits from the lower cost of NAND Flash as the storage solution and
the higher performance of DRAM as the XIP memory.
This technical note discusses a boot-from-NAND solution for applications using the
Texas Instruments™ (TI) OMAP2420 processor and the Micron® MT29F1G08ABB
NAND Flash device. The technical note provides a four-stage boot sequence. Stages 1
and 2 are independent of the operating system (OS); however, they are highly dependent
on system hardware. Thus, the primary focus of this technical note is on stage 1 and
stage 2 boot processes.
Additional system details:
• TI OMAP2420 H4 with processor daughter card “Menelaus ES 2.0”;
S/N: 750-0006, Rev C.
• The boot-from-NAND concepts discussed are OS independent; however, the Linux
OS is used as an example in some explanations.
Note that secure booting via the OMAP™ high-security (HS) device is not in the scope of
this document. However, NAND Flash booting for HS and GP differs only in the generation
of the X-Loader. Thus, the solution discussed here is generally applicable to both
the HS and GP processors.
solid-state storage media. Historically, NAND Flash has been used extensively in
applications such as mass storage cards and digital cameras. With its low cost and high
performance, NAND Flash is beginning to make its way into more complex embedded
systems where NOR Flash has dominated in the past—for example, in mobile phones.
In complex embedded systems, one of the challenges associated with a change from
NOR Flash to NAND Flash has been the boot process. NOR Flash has been a popular
choice for these systems because it contains a traditional memory interface (including
both address and data buses), making it capable of execute-in-place (XIP) operation. XIP
memory enables the system CPU to execute code directly from the memory device
because the boot code is stored on and executed from a single device.
NAND Flash is a page-oriented memory device that does not inherently support XIP, at
least not in the same manner as a typical XIP memory device. Operating system and
boot code can be stored in NAND Flash memory, but the code must be copied (or shadowed)
to DRAM before it can be executed. This requires system designers to modify the
boot process for their systems when using NAND Flash. The payoff for this modification
is that the system benefits from the lower cost of NAND Flash as the storage solution and
the higher performance of DRAM as the XIP memory.
This technical note discusses a boot-from-NAND solution for applications using the
Texas Instruments™ (TI) OMAP2420 processor and the Micron® MT29F1G08ABB
NAND Flash device. The technical note provides a four-stage boot sequence. Stages 1
and 2 are independent of the operating system (OS); however, they are highly dependent
on system hardware. Thus, the primary focus of this technical note is on stage 1 and
stage 2 boot processes.
Additional system details:
• TI OMAP2420 H4 with processor daughter card “Menelaus ES 2.0”;
S/N: 750-0006, Rev C.
• The boot-from-NAND concepts discussed are OS independent; however, the Linux
OS is used as an example in some explanations.
Note that secure booting via the OMAP™ high-security (HS) device is not in the scope of
this document. However, NAND Flash booting for HS and GP differs only in the generation
of the X-Loader. Thus, the solution discussed here is generally applicable to both
the HS and GP processors.
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