ARM Architecture Overview(I)

• ARM Operating Modes
– User mode: a normal program execution state
– FIQ – Fast Interrupt: for fast interrupt handling
– IRQ – Normal Interrupt: for general purpose interrupt handling
– Supervisor mode (SVC): a protected mode for operating system
– Abort mode: when a data or instruction pre-fetch is aborted
– Undefined mode: when an undefined instruction is executed
– System mode: a privileged user mode for the operating system
• ARM Processor States
– Arm state: all instructions are 32bits long, word-aligned.
– Thumb state: all instructions are 16 bits wide, half-word aligned.
– Jazelle state: all instructions are 8 bits wide for Java Bytecode
(for v5TEJ only)
• ARM Exception Types
– Reset
• Hardware reset: when the processor reset pin is asserted
• Software reset: by branching to the reset vector (0x0000)
– Undefined instruction
• the processor cannot recognize the currently execution instruction
– Software Interrupt (SWI)
• By s/w instruction, to allow a program running in User mode to
request privileged operations that are in Supervisor mode
– Prefetch Abort
• Fetch an instruction from an illegal address
– Data Abort
• A data transfer instr. try to load or store data at an illegal address
– IRQ: The processor IRQ pin is asserted and the I bit in CPSR is clear
– FIQ: The processor FIQ pin is asserted and the F bit in CPSR is clear